
Roviero
Revolutionizing electric vehicle charging infrastructure.
Date | Investors | Amount | Round |
---|---|---|---|
$6.6m | Seed | ||
Total Funding | 000k |
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Roviero is a Silicon Valley-based deep-tech startup targeting the edge artificial intelligence (AI) compute market. Founded in 2019 by industry veterans and serial entrepreneurs Deepak Mital, Sumat Mehra, and Ravi Setty, the company develops semiconductor IP and software to enable AI processing on edge devices. The founding team's collective experience in the semiconductor and AI industries underpins the company's approach to creating power-efficient processing solutions. In February 2021, Roviero secured $6.6 million in an oversubscribed seed funding round led by Great Point Ventures, with participation from Monta Vista Capital and Dolby Family Ventures, to expand its development efforts.
Roviero's business model centers on licensing its intellectual property (IP) and software stack to semiconductor companies and original equipment manufacturers (OEMs). The company's main offering is a full-stack AI accelerator solution that includes both hardware design and the necessary software for implementation. This approach allows clients to integrate Roviero's technology into their own System on Chip (SoC) designs, facilitating natively intelligent devices like cameras, IoT products, mobile phones, and computers. By providing FPGA-based platforms, Roviero enables customers to start developing applications before their final SoC is ready, potentially shortening time-to-market.
The company's flagship product is the CortiOne™ Neural Processing Unit (NPU), complemented by the CortiSoft™ compiler technology. This hardware and software combination is engineered for high performance with ultra-low power consumption and low latency, which are critical for edge devices. The CortiCore™ processor architecture is designed for power efficiency and can scale from under one to over 500 TOPS (trillion operations per second). A key feature is the inclusion of an Arm Cortex-M core deep within the NPU, offering the flexibility to support future neural network requirements. This hybrid design simplifies compiler complexity and improves hardware utilization, aiming to address scalability and programmability challenges in edge AI.
Keywords: edge AI, AI accelerator, neural processing unit, NPU, semiconductor IP, system on chip, SoC, low-power AI, AI inference, graph processor, CortiOne, CortiSoft, deep-tech, computer vision, IoT devices, intelligent edge, hardware-software co-design, AI compute, embedded systems, machine learning