Oasys Design Systems

Oasys Design Systems, established in 2004, operated in the electronic design automation (EDA) sector, providing specialized software for chip design. The company was founded in Santa Clara, CA, by a team of RTL synthesis veterans: Paul van Besouw, Johnson Limqueco, and Harm Arts. This founding team had previously formed the core R&D group at Ambit Design Systems, which was later acquired by Cadence. Their collective experience in physical synthesis was pivotal in shaping Oasys's direction.

The firm's core offering was its Chip Synthesis™ platform, a technology developed to address the design and implementation of large, complex integrated circuits (ICs) exceeding 20 million gates. The flagship product, RealTime Designer™, launched in 2009, introduced a next-generation physical RTL (Register Transfer Level) synthesis platform. This technology targeted the critical challenges of timing, power, area, and routability (PPA) in advanced System-on-a-Chip (SoC), ASIC, and IP block designs. Oasys's patented "placement first" synthesis methodology and integrated RTL floorplanning were key differentiators, allowing physical backend issues to be analyzed and resolved much earlier in the design cycle. This approach enabled faster turnaround times and gave the software the capacity to synthesize the entire top level of very large designs.

Oasys served leading-edge semiconductor and systems companies worldwide, including notable clients like Renesas in Japan. Its business model centered on licensing its proprietary EDA software tools to these high-tech firms. The company secured funding from prominent investors within the semiconductor industry, including Intel Capital, Xilinx, Band of Angels, and former Cadence CEO Joe Costello. Total funding reached approximately $7.92 million across several rounds. In December 2013, Oasys Design Systems was acquired by Mentor Graphics, which sought to integrate the RealTime RTL physical synthesis platform into its own digital implementation flow to enhance its offerings for advanced nodes.

Keywords: electronic design automation, EDA, RTL synthesis, chip design software, physical synthesis, SoC design, ASIC implementation, integrated circuit design, semiconductor design tools, Oasys Design Systems, Paul van Besouw, RealTime Designer, placement first synthesis, RTL floorplanning, Mentor Graphics acquisition, Intel Capital, Xilinx, chip synthesis, PPA optimization, IC implementation