Chip Path Design Systems
closedFPGA, FPASSP and SOC web portals to do chip architectures; eg searching, selecting and comparing FPGA devices from different vendors.
| Date | Investors | Amount | Round |
|---|---|---|---|
| investor investor | €0.0 | round | |
$4.9m | Series A | ||
| Total Funding | 000k | ||
Chip Path Design Systems operates in the Electronic Design Automation (EDA) and Semiconductor IP sectors, focusing on merging these two fields to streamline the integrated circuit (IC) design process. The company was established in November 2010 by J. George Janac, an experienced figure in the EDA industry, who serves as CEO and Chairman. A significant milestone occurred in December 2010 when the firm secured $3 million in a Series A funding round from investors including Scientific Ventures, Lanza techVentures, and Xilinx Corporation. This initial funding was aimed at accelerating product delivery and building out distribution channels.
The company's core business revolves around providing architectural design tools for the front-end of the chip design process, from specification and IP assembly to physical planning. Chip Path targets designers of Application-Specific Integrated Circuits (ASICs) and those compiling designs for Field-Programmable Gate Array (FPGA) and Application-Specific Standard Product (ASSP) devices. Its business strategy centers on what it terms "Semantic-IC Design," which aims to transform how companies architect integrated circuits. The product, ChipArchitect, is a web-based tool that allows engineers to create a design architecture, estimate its parameters, and map it to various technologies, including System-on-Chip (SoC) and FPGA devices. The platform supports numerous FPGA families and provides features for searching and selecting components, even linking to distributor inventory for procurement. It enables architects to work with semantic or placeholder IP, vendor IP, or internal IP to assemble and evaluate the economic feasibility of their designs.
Keywords: Electronic Design Automation, Semiconductor IP, ASIC design, FPGA design, Semantic-IC Design, ChipArchitect, SoC architecture, front-end design tools, IP assembly, physical planning, J. George Janac, circuit design software, chip architecture, design planning, semiconductor front-end, EDA tools, ASIC interoperability, FPGA interoperability, design estimation, web-based EDA